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 Integrated Device Technology


  • 9DBU0441 4-output 1.5 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer with Zo=100 ohms

  • Created: May 17, 2016

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Description

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Summary

The 9DBU0441 is a zero delay/ fanout clock buffer offered byIDT. This device is a member of their 1.5V Ultra-Low-Power (ULP) PCIe family. The ULP devices are the newest addition to their portfolio of PCIe Gen1, Gen2, and Gen3 solutions. They consume less than 50mW of power, that is less than 1/10th of the power required by previous solutions.


The 9DBU0441 clock buffer has 100Ω impedance at its integrated output terminations to make direct connection to 100Ω transmission lines possible. It has four outputs that can deliver 1-167MHz low power HCSL (High Speed Current Steering Logic) DIF pairs with Zo=100Ω. The device has also four output enables for its clock management and three selectable SMBus addresses, which helps optimize signal integrity and multiple devices sharing. The input to the device is HCSL compatible and can be driven by common clock sources. The device can be operated with a 1.5V, which is supplied to power pins of differential input clock power, digital power, output power and PLL core power (VDDR1.5, VDDDIG1.5, VDDO1.5 and VDDA1.5). The 9DBU0441 only consumes 45mW at typical conditions in PLL mode.


The 9DBU0441 comes also with key specifications that can be helpful in designing an application with this product. Some of this are DIF cycle-to-cycle jitter, which is less than 50ps, DIF output-to-output skew which is less than 75ps and DIF bypass mode additive phase jitter, which is less than 300fs for PCIe Gen3 and less than 350fs for 12khz-20MHz.