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 Integrated Device Technology

  • 9DBU0231 - 2-output 1.5 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

  • Created: May 12, 2016

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The 9DBU0231 device is a dual output zero delay/fan-out buffer. It is a member of IDT’s Ultra-Low-Power (ULP) PCIe family. The 9DBU0231 has two outputs designed for clock management. It runs with a 1.5V power supply and typically consumes 0.035W of power in PLL mode.

The 9DBU0231 has a single differential input that accepts frequency ranging from 1MHz up to 167MHz when it operates in bypass mode. In PLL mode, the input frequency is typically 100MHz. The ^VHIBW_BYPM_LOB trilevel input pin determines the PLL operating mode. The DIF pair 0 (DIF0, DIF0#) and DIF pair 1 (DIF1, DIF1#) are the two differential clock outputs of this device. It is enabled or disabled by pins OE0# and OE1#. The pins OE0# and OE1# are active low inputs. They are internally pulled down, so by default the differential outputs are enabled. The power mode of the 9DBU0231 device depends on the ^CKPWRGD_PD# pin. A low input in this pin makes the device enter into power down mode, while a high input exits the device from power down mode. By default, the device is out of power down mode since this pin is internally pulled up.

A simple two-wire system management bus (SMBus) is included in the design of the 9DBU0231 device. The slew rate for each output as well as the amplitude of the output can be controlled through this bus. The mode and the bandwidth of the PLL can be also set through the SMBus. This SMBus interface is 3.3V tolerant and works with legacy controllers. The 9DBU0231 is ideal to be used as a zero delay/fan-out buffer for PCIe generation 1, 2, and 3 application.