5P49V6901 VersaClock 6 Programmable Clock Generator
Created: May 10, 2016
No description available.
A programmable clock generator is a device that replaces crystals, oscillators and buffers as a single timing device in electronic circuits. Using this device, allows designers to save space in circuit boards and lower cost in their designs. This timing solution is very much appropriate in telecommunications, data communications, computing applications and consumer products.
This reference design uses the 5P49V6901, one of the programmable clock generators from IDT that comes with the sixth generation of programmable clock technology (VersaClock6). Having this technology, the device is expected to function at a very high performance with low power consumption. Configurations for this device can be stored in its on-chip One-Time Programmable memory or changed using I2C interface. It can generate up to four independent output frequencies. These frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. The CLKSEL pin selects the input clock between either XTAL/REF or (CLKIN, CLKINB). Either clock input can be set as the primary clock. The primary clock designation is to establish which is the main reference clock to the PLL. The non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation. The device may be configured to use one of two I2C addresses to allow multiple devices to be used in a system.
This circuit is a typical application diagram for 5P49V6901. The circuit shown is operated at VDDD and VDDA = 1.8V but could also use 2.5V and 3.3V as its core voltage. As with any high-speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The clock generator provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. It is also recommended that the filter capacitors be placed as close to the power pins to achieve best possible filtering. The input and output terminations shown in the diagram are intended for reference and may not represent the final configuration of the user. The OUT1 to OUT4 clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register; any of these outputs can support LVCMOS, LVPECL, HCSL or LVDS logic levels. Configuration of different logic level output termination is shown in the diagram.